7세그먼트 디코더 vhdl 중인데요... 토할꺼 같아요 제발 도와주세요
도대체 왜 왜왜왜왜 에러가 뜨죠 하 몇번을 지우고해도 무한 에러
하다하다 지쳐서 도움 요청합니다..
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity lab is
port( clk : in std_logic;
key : in std_logic_vector(15 downto 0);
seg : out std_logic_vector(6 downto 0));
end lab;
architecture design of lab is
begin
-- process for key input
process(clk, key)
begin
if rising_edge(clk) then
case key(15 downto 0) is
when "0000000000000001" => seg <= "1111110";
when "0000000000000010" => seg <= "0110000";
when "0000000000000100" => seg <= "1101101";
when "0000000000001000" => seg <= "1111001";
when "0000000000010000" => seg <= "0110011";
when "0000000000100000" => seg <= "1011011";
when "0000000001000000" => seg <= "1011111";
when "0000000010000000" => seg <= "1110000";
when "0000000100000000" => seg <= "1111111";
when "0000001000000000" => seg <= "1110011";
when "0000010000000000" => seg <= "1111101";
when "0000100000000000" => seg <= "0011111";
when "0001000000000000" => seg <= "0001101";
when "0010000000000000" => seg <= "0111101";
when "0100000000000000" => seg <= "1101111";
when "1000000000000000" => seg <= "1000111";
when others => null;
end case;
end if;
end process;
end design;
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